Island Scaling Effects on Photoluminescence of Strained SiGe/Si (100)

The fabrication of electronic devices on semiconductor islands is becoming increasingly common because of silicon-on-insulator technology and/or because of strain engineering in compliant substrate approaches. While photoluminescence can be an accurate probe of Ge content and strain, in islands it can be affected by the presence of the island edges. Here we present data and a model showing that for high quality SiGe, edge effects are critical for sizes under ~20 μm. These effects can be mitigated by regrowing epitaxial silicon to passivate the recombination states on the island edges. INTRODUCTION A recent trend in advanced transistor technologies is the fabrication of devices on semiconductor islands or mesas. Silicon-on-insulator (SOI) technology is increasingly popular because of its lower voltage/power and higher speed capabilities compared to traditional bulk Si. When combined with trench isolation between devices, SOI often yields silicon islands. High mobility channel techniques also often utilize islands. For example, strain engineering on compliant substrates [1], crystal-orientation engineering [2], and some novel device structures [3] all require the use of islands. Photoluminescence (PL) is a useful and non-destructive means of characterizing epitaxial layer strain and quality as well as alloy content. When used on island structures, however, the island edges may affect the photoluminescence spectrum. This work experimentally investigates these island edge effects, proposes a model to explain and fit the results, and demonstrates a way to partially mitigate the edge effects. EXPERIMENT Silicon (Si) and silicon-germanium (SiGe) epitaxial layers were grown by rapid-thermal chemical vapor deposition. Using an HF-last process, an n-type silicon (100) substrate is wetcleaned and then cleaned in situ with a high-temperature, high-pressure (250 Torr) bake in hydrogen ambient. A ~1 μm silicon buffer layer is grown at a pressure of 6 Torr with 3 lpm (liters per minute) hydrogen carrier flow and 4.33x10 ms dichlorosilane, at a temperature of approximately 1000C. The growth continues with a pseudomorphic ~10 nm Si0.8Ge0.2 layer, capped with a ~13 nm silicon layer, as shown in figure 1(a). The compressively strained SiGe layer is grown at 625C using dichlorosilane and 0.8% germane in hydrogen, and the strain-free silicon cap is grown at 700C using dichlorosilane in hydrogen. Further growth details can be found in reference 4. Square island arrays are dry-etched using SF6 and O2. The island edge lengths measure from 5 to 500 μm with inter-island spacings of 1 to 20 μm, respectively. An array of 20 μm islands is B8.4.1 Mat. Res. Soc. Symp. Proc. Vol. 809 © 2004 Materials Research Society